This invention relates to providing determinism in a multiprocessor computer system, to a monitor and processor for such a system and to a method of operating such systems. A particular application of the invention is to fault tolerant processing systems.
Many processing systems operate to a strict timing regime, changing their internal state on a known clock. Such a synchronous design of a processing system results in a large finite state machine. The internal state and outputs of this machine are entirely predictable, if inputs are presented in a known relationship to the clock. This determinism enables the construction of a fault tolerant multi-computer system by providing checking hardware, which compares the operation of one processor or set of processors against that of another identical processor or set of processors. The checking hardware can be arranged to check for faults in the operation of one or more of the processing sets by comparing the outputs of those processing sets on each clock.
Other processing systems do not behave in such a simple manner. Examples of this type are processing systems where the clock is not known, where multiple unrelated clocks are used, or where processor operation uses no clocks at all. These processing systems cannot be modelled as synchronous finite state machines. It may not be possible to present inputs to these processing systems in any known relationship to the computer's internal state. The detailed operation of these machines is non-deterministic. This prevents ordinary construction of checking hardware to compare operation between identical systems.
An aim of the present invention is to enable the provision of a deterministic multiprocessor system where at least one processor, or set of processors, operates asynchronously of another processor or set of processors.